The present invention relates to an electrically writable and erasable non-volatile semiconductor memory device such as a flash memory or the like.
In recent years, an electrically writable and erasable non-volatile semiconductor memory device (a so-called flash memory) having a plurality of memory cells provided with a floating gate which is an electric load accumulation layer between a gate and a channel is widely used for a data storage of a digital still camera, a digital audio device and a flash card or the like because the cost thereof is low and the device has an electrically erasing function. In such a flash memory, an increase in the capacity is conventionally demanded together with a high-speed rewriting operation. As one of the technique of attempting an increase in the capacity, a multiple-value technique is known. In a binary value flash memory, a threshold value voltage of the memory cell in slow state is set to xe2x80x9c1xe2x80x9d (or xe2x80x9c0xe2x80x9d) whereas the threshold value voltage of the memory cell in a high state is set to xe2x80x9c0xe2x80x9d (or xe2x80x9c1xe2x80x9d). On the other hand, in the flash memory using the multiple-value technique (hereinafter referred to as a multiple-value flash memory), the flash memory is controlled so that the threshold value voltage of the memory cell is allowed to correspond to the three or more state.
For example, in order to memorize four values, the threshold value voltage of the memory cell is set to four states so that the four states to correspond to xe2x80x9c11xe2x80x9d, xe2x80x9c10xe2x80x9d, xe2x80x9c00xe2x80x9d, and xe2x80x9c01xe2x80x9d, respectively. Here, let xe2x80x9c11xe2x80x9d correspond to the lowest state of the threshold value voltage, and xe2x80x9c01xe2x80x9d correspond to the highest state of the threshold value voltage. As a result, it becomes possible to memorize two bits data in one memory cell.
FIGS. 13 and 14 are views showing one example of a threshold value voltage regulated in accordance with each data added to the memory cell of the multiple-value flash memory. In this example, the threshold value in the lowest state corresponding to xe2x80x9c11xe2x80x9d is regulated to VF0 through VFU0 (for example, 1V through 1.7V), the threshold value voltage in the state corresponding to xe2x80x9c10xe2x80x9d is regulated to VF1 through VFU1 (for example, 2.3V through 2.7V), the threshold value voltage corresponding to xe2x80x9c00xe2x80x9d is regulated to VF2 through VFU2 (for example, 3.3 V through 3.7 V) and the threshold value voltage corresponding to xe2x80x9c01xe2x80x9d is regulated to VF3 or more (for example, 4.3V or more).
In this manner, in the multiple-value flash memory, a plurality of threshold value voltages corresponding to each data are regulated in parallel. In such a case, it is necessary to control the threshold value voltage of the memory cell with good precision as compared with the case in which the conventional binary value flash memory is used.
FIG. 15 shows a procedure of a writing operation in the conventional multiple-value flash memory. When the writing operation starts, the data is input (S51). After the input of the data, a writing pulse (for example, 18V) is applied to the memory cell in which the state of xe2x80x9c01xe2x80x9d is to be written (S52). Then, the writing verify is conducted at the voltage of VF3 along with the application of this writing pulse (S53). In this writing verify, the data in the memory cell is read by the application of the predetermined verify voltage to, for example, the word line voltage, so that judgment is made as to whether or not the data is normally written by the comparison of this read data with the data to be written. Such a writing pulse application and writing verify are repeated in an interval until judgment is made that the data is normally written. When the verify operation is passed with respect to all the memory cells until the predetermined times are attained (for example, ten times), the process proceeds to the application of the writing pulse of xe2x80x9c00xe2x80x9d (S54). However, the writing pulse is prevented from being applied to the memory cell which has a threshold value voltage of VF3 or more. On the other hand, in the case where the writing verify is not passed even when the predetermined times are attained, namely, in the case of the presence of the memory cell having the threshold value of not more than VF3, time is over and error end is generated.
At steps S54 and S55, and S56 and S57, the writing pulse application and the writing verify are executed in the same manner as the state of xe2x80x9c01xe2x80x9d described above with respect to the states of xe2x80x9c00xe2x80x9d and xe2x80x9c01xe2x80x9d, respectively.
When the application of the writing pulses of xe2x80x9c01xe2x80x9d, xe2x80x9c01xe2x80x9d, and xe2x80x9c10xe2x80x9d and the writing verify are normally completed at steps S52 through S57, the upper sleeve verify operation in the state of xe2x80x9c11xe2x80x9d, xe2x80x9c10xe2x80x9d and xe2x80x9c01xe2x80x9d is subsequently executed (S58 through S60). The upper sleeve verify is an operation of detecting a memory cell whose threshold value voltage becomes too high. When the upper sleeve verify is passed with respect to all the xe2x80x9c11xe2x80x9d, xe2x80x9c10xe2x80x9d and xe2x80x9c00xe2x80x9d, the writing operation is normally completed. On the other hand, for example, in the case where the threshold value voltage of the memory cell which should be in the state of xe2x80x9c00xe2x80x9d becomes VFU2 or more, the upper sleeve verify is recognized as xe2x80x9cwriting failure (hereinafter referred to as a fail)xe2x80x9d to judge whether or not the fail is the second time (S61). When the fail is the first time, an erasure is executed (S62). After the threshold value voltage of the memory cell in the sector is brought back to the state of xe2x80x9c11xe2x80x9d, the writing operation same as the first time is executed again from S52.
Next, an erasure operation in the conventional multiple-value flash memory will be explained by referring to FIGS. 16 and 17. FIG. 16 is a view showing a part of a relation between the threshold value voltage and the verify voltage of the memory cell in the erasure state. FIG. 17 is a flowchart showing the above erasure operation. The erasure operation in the multiple-value flash memory is the same as the case of the binary-value flash memory. When the erasure operation starts, an erasure pulse, which is a negative high voltage is applied (S71). Along with the application of the erasure pulse, an erasure verify is executed to judge whether or not the threshold value voltage of the memory cell becomes a predetermined verify voltage (for example, VER which is 1.6V) or less as shown in FIG. 16 (S72). The erasure pulse application and the erasure verify are repeated in an interval until judgment is made that data erasure is normally executed. When the verify operation is passed with respect to all the memory cells until predetermined times are attained (for example, ten times), the process proceeds to the deplete check (S73) On the other hand, in the case where the erasure verify is not passed even if the predetermined times are attained, namely, in the case where the memory cells are present which have the threshold value of VER or less, time is over and error end is generated.
In the deplete check of S73, judgment is made as to whether there is any memory cell whose threshold value voltage has become too low (VF0). When this deplete check is passed, the erasure operation is normally ended. When judgment is made that the deplete check is NG, the write-back pulse of xe2x80x9c11xe2x80x9d is applied so that the threshold value voltage of the memory cell becomes VF0 or more (S74) Along with the application of this write-back pulse, the write-back verify is conducted for judging whether or not the threshold value voltage of all the memory cells is VF0 or more (S75). When the write-back verify is passed, the upper sleeve verify of xe2x80x9c11xe2x80x9d is subsequently executed (S76), so that the memory cell which has the threshold voltage of VF0 or more is detected. In the case where judgment is made that the upper sleeve verify of xe2x80x9c11xe2x80x9d is OK, the operation is normally ended. On the other hand, in the case where judgment is made that upper sleeve verify is a fail, judgment is made as to whether the fail is the second time or not (S77). In the case where the fail is the first time, the erasure operation same as the first time is conducted from S71 again.
By the way, in order to control the threshold value voltage of the memory cell to a predetermined scope in the writing operation, it is necessary to repeat a relatively short time writing pulse application and the writing verify. Normally, in accordance with this, as shown in FIG. 18, the writing is executed in a relatively short pulse, and gradually longer writing pulse is applied with the result that the threshold value voltage can be controlled in a good precision, and the total writing time can be shortened. However, for all that, there sometimes arises a case in which the threshold value voltage of the memory cell cannot be controlled within the predetermined scope because of the irregular behavior. For example, in FIG. 14, in the case where the threshold value voltage becomes VFU2 or more with respect to the threshold value voltage of only one memory cell which is written in the state of xe2x80x9c00xe2x80x9d, the fail is generated in the upper sleeve verify of xe2x80x9c00xe2x80x9d so that rewriting is executed after the sector erasure has been executed. When the rewriting is executed, the memory is passed in most cases, and the fail is rarely generated again. In this case, error end is generated.
In order to suppress writing failure, there is considered a method for further shortening the time of one time writing pulse application and setting to a low level the threshold value voltage of the memory cell so that a variation in the threshold value voltage of the memory cell by the one time writing pulse application is reduced. However, in the case where such a method is used, it takes a long time until the writing operation is normally completed. Such a problem can be applied to the case of write-back pulse application of xe2x80x9c11xe2x80x9d at the time of the erasure operation.
The present invention has been made in view of the above technical problems, and an object of the invention is to provide a non-volatile semiconductor memory device which is capable of shortening the average time until the writing and erasure operation is normally completed and suppressing the failure rate of the writing and erasure operation.
According to a first aspect of the present invention, there is provided a non-volatile semiconductor device having a memory cell in which a threshold value voltage changes and the data corresponding to the threshold value voltage are written in response to application of the writing pulse having a predetermined width and voltage to word lines and bit lines, the device executing a verify operation for judging the data from the threshold value voltage every application of the writing pulse in the data writing operation, characterized in that: the writing condition is set which is capable of suppressing the writing failure rate than in the case of the first-time writing operation, when the writing failure is generated in the first-time writing operation and the writing operation is re-executed. Furthermore, the initial value of the writing pulse width may be set to a level smaller than the value at the first-time writing operation when the writing operation is re-executed. Furthermore, an increase rate of the writing pulse width may be set to a smaller level than the first-time writing operation when the writing operation is re-executed.
Still furthermore, the writing pulse width may be set to an equal width with respect to a predetermined number of writing pulses after the start of the writing pulse application when the writing operation is re-executed. Furthermore, the writing pulse voltage may be set to a smaller level than the first-time writing operation when the writing operation is re-executed.
Still furthermore, the reference scope of the threshold value voltage used at the above verify time may be set to a larger level than the first-time writing operation when the writing operation is re-executed. Furthermore, the voltage level forming the upper limit of the reference scope of the threshold value voltage may be set to a level higher than the first-time writing operation. Still furthermore, the voltage level forming the lower limit of the reference scope of the threshold value voltage may be set to a level lower than the first-time writing operation.
Still furthermore, the corresponding relation between the data to be written and the threshold value voltage of the memory cell may be changed when the writing operation is re-executed. Furthermore, the corresponding relation between the memory cell in which data is written and the Y address of the data may be changed when the writing operation is re-executed.
The non-volatile semiconductor memory device may be further constituted in such a manner that the device applies a write-back pulse having a predetermined width and a voltage to set the threshold value voltage to a predetermined value or more in the case where the threshold value voltage of the memory cell becomes less than the predetermined value in the data erasure operation, and executes verify operation for judging data from the threshold value voltage every application of the writing pulse with the result that a write-back condition is set which is capable of suppressing the write-back failure rate than the first-time erasure operation in the same manner as the writing condition is capable of suppressing the writing failure than the first-time writing operation, when the write-back failure is generated in the first-time data erasure operation and the erasure operation is re-executed.